Monday, 11 September 2000

8.00 8.45

Registration

8.45 9.00

Opening Session

9.00 10.00

Invited lecture: Computational Aspects of Sensing, Modeling, and Visualizing the Real World

Takeo Kanade (USA)

10.00 11.15	Session: Vision Systems
1	A imaging library for a tricore based digital camera	A. Chihoub, Y.J. Bai and V. Ramesh USA
2	FreeTIV parallel computer: architecture and environment	F. Amiot and E. E. Pissaloux FRANCE
3	Active computer vision system	D. Paulus, Chr. Drexler, M. Reinhold, M. Zobel, and J. Denzler GERMANY

11.30 13.10	Session: VLSI Architectures
4	The Acadia vision processor	G. van Der Wal, M. Hansen, and M. Piacentino USA
5	Method of moment calculation for a digital vision chip system	I. Ishii, T. Komuro, and M. Ishikawa JAPAN
6	High speed target tracking vision chip	T. Komuro, I. Ishii, M. Ishikawa, and A. Yoshida JAPAN
7	A VLSI architecture for image sequence segmentation using edge fusion	J. Kim, and T. Chen USA

14.30 15.30

Invited lecture: Classical Processing on Arrays of Qubit

Pieter P. Jonker NETHERLANDS

15.30 16.45	Session: NEURAL NETWORKS
8	2-D Object recognition by structured neural networks in a pyramidal architecture	V.Cantoni, and A. Petrosino ITALY
9	A high speed flat CORDIC based neuron with multi-level activation function for robust pattern recognition	B. Gisuthan, T. Srikanthan, and K.V. Asari SINGAPORE
10	Parallel segmentation based on topology with the associative net model	D. Dulac, S. Guezguez, and G. Bertrand FRANCE

17.00 19.00	Poster Session
p1	The need and requirements of modular and scalable DSP-architecture for real-time opto-electronic part recognition system	A. Brenner AUSTRIA
p2	A genetically optimized artificial neural network structure for feature extraction and classification of vascular tissue fluorescence spectrums	G.A. Rovithakis, M. Maniadakis, and M. Zervakis GREECE
p3	An FPGA architecture for high speed edge and corner detection	C. Torres-Huitzil, and M. Arias-Estrada MEXICO
p4	Recovering 3-D egomotion parameters from optic flow: from structural principles to analog architectures	S. P. Sabatini, P. Cavalleri, F. Solari, and G. M. Bisi ITALY
p5	Space variant vision and pipelined architecture for time to impact computation	F. Pardo, I. Llorens, F.Mico, and J. A. Boluda SPAIN
p6	Multi-sensors and environment simulator for collision avoidance applications	S. Bouaziz, M. Fan, R. Reynaud, and T. Maurin FRANCE
p7	Fast stable matching algorithm using asynchronous parallel programming model	F. Verdier, A. Merigot, and B. Zavidovique FRANCE
P8	Fast retrieval on compressed image for internet application	M. G. Albanesi, and A. Giancane ITALY
p9	A VLSI Architecture for 2D Mesh-based Video Object Motion Compensation	W.Badawy , and M. Bayoumi USA

GET-TOGETHER PARTY (19.30)

Tuesday, 12 September 2000

9.00 10.00

Invited lecture: Trends in Scientific Computing

Paul Messina (USA)

10.00 11.15	Session: Architectures
11	A system-on-a-chip for pattern recognition. Architecture and design methodology	M. Aberbour, H. Mehrez, F. Durbin, J. Haussy, P. Lalande, and A. Tissot FRANCE
12	Notacheck: a parallel DSP-based architecture for real time high resolution inspection of banknotes	G. Coldani, L. Cotrino, G. Danese, F. Leporati, and M. Maneri ITALY
13	In the development and evaluation of specialized processors for computing high-order 2-D image moments in real-time	N. Roma, and L. Sousa PORTUGAL

11.30 13.10	Session: Distributed systems
14	A distributed system for real-time volume reconstruction	E. Borovikov, and L. Davis USA
15	A distributed architecture for autonomous navigation of robots	V. Di Gesu', B. Lenzitti, G. Lo Bosco, and D. Tegolo ITALY
16	Study of a parallel CBIR implementation using MPI	J. L. Bosque, O. D. Robles, A. Rodriguez, and L. Pastor SPAIN
17	Real-time computer vision on PC-cluster and its application to real-time motion capture	D. Arita, S. Yonemoto, and R. Taniguchi JAPAN

14.30 16.10	Session: Configurable Computing
18	FPGA-based coprocessor for text string extraction	N. K. Ratha, A. K. Jain, and D. T. Rover USA
19	Compiling and optimizing image processing algorithms for FPGA’s	B. Draper, W. Najjar, W. Bohm, J. Hammes, B. Rinker, C. Ross, M. Chawathe, and J. Bins USA
20	A configurable processor network for document management	S. Vagnier, H. Essafi, and A. Merigot FRANCE
21	How to use high speed reconfigurable FPGA for real time image processing?	D. Demigny, L. Kessal, R. Bourguiba, and N. Boudouani FRANCE

EXCURSION (16.30)

Wednesday, 13 September 2000

9.00 10.00

Invited lecture: Multi-media Extensions in Super-pipelined Micro-architectures. A new case for SIMD processing?

Marco Ferretti ITALY

10.00 11.15	Session: Programming Environments
22	Loop regularization for image and video processing on instruction level parallel architectures	N. Zingirian, and M. Maresca ITALY
23	Examples of image processing to benefit from an asynchronous implementation	E. Senn, and B. Zavidovique FRANCE
24	Anet: a programming environment for parallel image analysis	B. Ducourthial, A. Merigot, and N. Sicard FRANCE

11.30 13.10	Session: Hardware Supported Techniques
25	An array control unit for high performance SIMD arrays	M. C. Herbordt, J. Cravy, H. Zhang, C. Lin, and H. Rao USA
26	The long and winding road to high-performance image processing with MMX/SSE	G. Conte, S. Tommesani, and F. Zanichelli ITALY
27	Hardware prefetching techniques for cache memories in multimedia applications	R. Cucchiara, M. Piccardi, and A. Prati ITALY
28	Hardware-supported technique for detecting multi-corners in digital contours	A. Sluzek SINGAPORE

14.30 16.10	Session: Algorithms and Applications
29	Homography based parallel volume intersection: toward real-time volume reconstruction using active camera	T. Wada, S. Tokai, and T. Matsuyama JAPAN
30	Handling artifacts in digitally reproduced documents	L. Cinque, S. Levialdi, L. Lombardi, and S. Tanimoto ITALY-USA
31	Compressed-domain classification of texture images	B. Wilson, and M.A. Bayoumi USA
32	Fast stereo matching for the VIDET system using a general purpose with multimedia extensions	L. Di Stefano, and S. Mattoccia ITALY

16.25 18.00

Panel Session Trends in Computer Architectures