Publications

Home
Personal Info
Teaching
Publications
Book Chapter
  1. P. Olivo and M. Dalpasso,
    A BIST Scheme for Non-Volatile Memories,
    pp. 139-144, in ON-LINE TESTING FOR VLSI,
    edited by M. Nicolaidis, Y. Zorian and D. K. Pradan,
    published by Kluwer Academic Publishers, 1998
Journals
  1. M. Favalli and M. Dalpasso,
    Simulazione di guasti in circuiti integrati digitali ,
    Alta Frequenza,
    Vol. 4, N. 1, pp. 13-22, Gen.-Feb. 1992
  2. M. Dalpasso, M. Favalli, P. Olivo and B. Riccò,
    Fault Simulation of Parametric Bridging Faults in CMOS ICs ,
    IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems,
    Vol. CAD-12, pp. 1403-1410, September 1993
  3. M. Favalli, M. Dalpasso, P. Olivo and B. Riccò,
    Analysis of Resistive Bridging Fault Detection in BiCMOS Digital ICs,
    IEEE Transactions on VLSI Systems,
    Vol. 1, pp. 342-355, September 1993
  4. M. Dalpasso, M. Favalli, P. Olivo and J. P. Teixeira,
    Realistic testability estimates for CMOS ICs,
    IEE Electronics Letters,
    Vol. 30, N. 19, pp. 1593-1595, September 15th, 1994
  5. M. Dalpasso,
    Advanced Test Pattern Generation for CMOS IDDQ Testing,
    Alta Frequenza,
    Vol. 8, N. 2, pp. 57-59, Mar.-Apr. 1996
  6. M. Dalpasso, M. Favalli and P. Olivo,
    IDDQ Test Invalidation by Break Faults ,
    IEE Electronics Letters,
    Vol. 32, N. 11, pp. 994-995, May 23rd, 1996
  7. M. Favalli, M. Dalpasso and P. Olivo,
    Modeling and Simulation of Broken Connections in CMOS ICs ,
    IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems,
    Vol. 15, N. 7, pp. 808-914, July 1996
  8. M. Favalli and M. Dalpasso,
    Symbolic Handling of Bridging Fault Effects,
    Journal of Electronic Testing, Theory and Applications,
    Kluwer Academic Publishers,
    Vol. 10, N. 3, pp. 271-276, June 1997
  9. M. Dalpasso and M. Favalli,
    A Method for Increasing the IDDQ Testability ,
    IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems,
    Vol. 16, N. 10, pp. 1186-1188, October 1997
  10. P. Olivo and M. Dalpasso,
    A BIST Scheme for Non-Volatile Memories,
    Journal of Electronic Testing, Theory and Applications,
    Kluwer Academic Publishers,
    Vol. 12, N. 1/2, pp. 139-144, February/April 1998
  11. M. Dalpasso, A. Bogliolo and L. Benini,
    Virtual Simulation of Distributed IP-based Designs,
    IEEE Design & Test of Computers,
    Vol. 19, N. 5, pp. 92-104, September/October 2002
  12. M. Favalli and M. Dalpasso,
    Bridging Fault Modeling and Simulation for Deep Submicron CMOS ICs,
    IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems,
    Vol. 21, N. 8, pp. 941-953, August 2002
  13. M. Dalpasso, G. Lancia and R. Rizzi,
    The String Barcoding Problem is NP-Hard,
    Lecture Notes in Computer Science,
    Vol. 3678 / 2005, pp. 88-96
  14. M. Favalli and M. Dalpasso,
    How many Test Vectors We Need to Detect a Bridging Fault?,
    Journal of Electronic Testing, Theory and Applications,
    Kluwer Academic Publishers,
    Vol. 25, N. 1, pp. 79-95, February 2009
  15. M. Favalli and M. Dalpasso
    Applications of Boolean Satisfiability to Verification and Testing of Switch-Level Circuits,
    Journal of Electronic Testing, Springer,
    Vol. 30, N. 1, pp. 41-55, Febbraio 2014
  16. L. Valenti, M. Dalpasso and M. Favalli,
    Efficient testing of multi-output combinational cells in nano-complementary metal oxide semiconductor integrated circuits ,
    IET Computers & Digital Techniques,
    Vol. 8, N. 2, pp. 83-89, March 2014
  17. M. Dalpasso and G. Lancia,
    Estimating the strength of poker hands by integer linear programming techniques,
    Central European Journal of Operations Research,
    Vol. 23, N. 3, pp. 625-640, Settembre 2015
  18. M. Favalli and M. Dalpasso,
    Boolean and Pseudo-Boolean Test Generation for Feedback Bridging Faults,
    IEEE Transactions on Computers,
    Vol. 65, N. 3, pp. 706-715, March 2016
Conferences with Proceedings
  1. M. Dalpasso, M. Favalli, P. Olivo and B. Riccò,
    Switch-Level Fault Simulation by Critical-Path Tracing ,
    IEEE European Test Conference,
    pp. 181-190, April 1991
  2. M. Ambanelli, M. Favalli, M. Dalpasso, P. Olivo and B. Riccò,
    Fault Simulation of Multiple Faults in PLAs,
    IEEE Annual European Computer Conference (CompEuro),
    pp. 229-232, May 1991
  3. M. Favalli, S. Ercolani, M. Dalpasso, P. Olivo and B. Riccò,
    Weighted Pseudorandom Generation for Built-In Self-Test ,
    IEEE Annual European Computer Conference (CompEuro),
    pp. 572-574, May 1991
  4. M. Favalli, M. Dalpasso, P. Olivo and B. Riccò,
    Analysis of Steady State Detection of Resistive Bridging Faults in BiCMOS Digital ICs,
    IEEE International Test Conference,
    pp. 466-475, September 1992
  5. M. Dalpasso, M. Favalli, P. Olivo and B. Riccò,
    Parametric Bridging Fault Characterization for the Fault Simulation of Library-Based ICs,
    IEEE International Test Conference,
    pp. 486-495, September 1992
  6. M. Dalpasso, M. Favalli, P. Olivo and B. Riccò,
    Influence of IC synthesis on the Random Pattern Testability of Parametric Bridging Faults,
    IEEE European Test Conference,
    pp. 398-407, April 1993
  7. M. Favalli, M. Dalpasso, P. Olivo and B. Riccò,
    Analysis of Dynamic Effects of Resistive Bridging Faults in CMOS and BiCMOS Digital ICs,
    IEEE International Test Conference,
    pp. 865-874, October 1993
  8. M. Favalli, M. Dalpasso, P. Olivo and B. Riccò,
    Modeling of Broken Connections Faults in CMOS ICs ,
    IEEE European Design and Test Conference,
    pp. 159-164, February-March 1994
  9. M. Dalpasso, M. Favalli and P. Olivo,
    Correlation between IDDQ Testing Quality and Sensor Accuracy,
    IEEE European Design and Test Conference,
    pp. 568-572, March 1995
  10. M. Dalpasso, M. Favalli and P. Olivo,
    Test Pattern Generation for IDDQ: Increasing Test Quality ,
    IEEE VLSI Test Symposium,
    pp. 304-309, April-May 1995
  11. M. Dalpasso and M. Favalli,
    Binary Decision Diagrams (BDDs) for the Test Pattern Generation,
    IEE International Conference on Software for Electrical Engineering Analysis and Design,
    pp.95-104, May 1996
  12. P. Olivo and M. Dalpasso,
    Self-Learning Signature Analysis for Non-Volatile Memory Testing,
    IEEE International Test Conference,
    pp. 303-308, October 1996
  13. M. Dalpasso, A. Bogliolo and L. Benini,
    Specification and validation of distributed IP-based designs with JavaCAD,
    IEEE/ACM Design Automation and Test in Europe Conference,
    pp. 684-688, March 1999
  14. M. Dalpasso, A. Bogliolo and L. Benini,
    Virtual Simulation of distributed IP-based designs ,
    IEEE/ACM Design Automation Conference,
    pp. 50-55, June 1999
  15. M. Dalpasso, A. Bogliolo L. Benini and M. Favalli,
    Virtual Fault Simulation of distributed IP-based designs ,
    IEEE/ACM Design Automation and Test in Europe Conference 2000,
    pp. 99-103, March 2000
  16. M. Dalpasso, A. Bogliolo and L. Benini,
    Hardware/Software IP protection,
    IEEE/ACM Design Automation Conference 2000,
    pp. 593-596, June 2000
  17. M. Favalli and M. Dalpasso,
    An evolutionary approach to the design of on-chip pseudorandom test pattern generators,
    IEEE/ACM Design Automation and Test in Europe Conference 2002,
    March 2002
  18. F. Bombi, G. Clemente, S. Congiu, M. Dalpasso, F. Filira, M. Furin, M. Moro, M. Sgargetta and R. Verago,
    A new multimedia distributed system for on-line advanced teleteaching,
    International Conference ICL (Interactive Computer Aided Learning),
    September 2005
  19. F. Bombi, G. Clemente, S. Congiu, M. Dalpasso, F. Filira, M. Furin, M. Moro, M. Sgargetta and R. Verago,
    A new multimedia distributed system for live teaching,
    Iadat-e2006 - 3rd International Conference on Education,
    July 2006
  20. F. Bombi, G. Clemente, S. Congiu, M. Dalpasso, F. Filira, M. Furin, M. Moro, M. Sgargetta and R. Verago,
    Live teaching with an advanced multimedia distributed system,
    IODL2006 - 2nd International Open & Distance Learning Symposium,
    September 2006
  21. M. Favalli and M. Dalpasso,
    High Quality Test Vectors for Bridging Faults in the Presence of IC's Parameters Variations
    ,
    22nd IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT '07),
    pp. 448-456, September 2007
  22. F. Filira, N Anghelidis and M. Dalpasso,
    Tele-Assessment of the Tele-Taught University Degree in Computer Science Engineering,
    iLearning Forum 2008,
    2008
  23. F. Filira, G. Boccuzzo, M. Dalpasso and N. Anghelidis,
    Effectiveness assessment of tele-taught vs. traditional courses of a 3-year university degree in compuoter science engineering
    ,
    INTED2008 International Conference,
    March 2008
  24. M. Dalpasso and G. Lancia,
    Computing the equity of a poker hand by Integer Linear Programming,
    International Symposium on Operational Research 2013,
    September 2013
Conferences without Proceedings
  1. M. Dalpasso,
    Approaching the Synthesis for Testable Circuits Beyond the Stuck-At Fault Model,
    ARCHIMEDES Open Workshop on Synthesis of Testable Circuits ,
    Bologna, Italy, February 1994
  2. M. Dalpasso,
    IDDQ Testing di circuiti integrati CMOS,
    ELETTRONICA 95 -- Riunione Annuale del Gruppo di Elettronica del CNR,
    Riva del Garda, Trento, Italy, June 1995
  3. P. Olivo and M. Dalpasso,
    Self-Learning Signature Analysis for Non-Volatile Memory Testing,
    IEEE European Test Workshop,
    Montpellier, France, June 1996
  4. P. Olivo and M. Dalpasso,
    A BIST Scheme for Non-Volatile Memories,
    IEEE International On-Line Testing Workshop,
    Biarritz, France, July 1996
  5. P. Olivo and M. Dalpasso,
    A BIST Scheme for Non-Volatile Memories,
    IEEE Non-Volatile Semiconductor Memory Workshop,
    Monterey, California, USA, February 1997
  6. G. Lancia, M. Dalpasso e R. Rizzi,
    The String Barcoding Problem is NP-Hard,
    RECOMB 2005 Satellite Workshop on Comparative Genomics,
    Settembre 2005
Thesis for Laurea Degree in Electronic Engineering
Simulazione a livello switch di circuiti integrati CMOS,
February 21st, 1990, Bologna, Italy.
Thesis for Ph.D. in Electronic Engineering and Computer Science
Analisi, Modellistica e Simulazione di Guasto in Circuiti Integrati CMOS,
July 25th, 1994, Rome, Italy.