
 Book Chapter
 P. Olivo and M. Dalpasso,
A BIST Scheme for NonVolatile Memories,
pp. 139144, in ONLINE TESTING FOR VLSI,
edited by M. Nicolaidis, Y. Zorian and D. K. Pradan,
published by Kluwer Academic Publishers, 1998
 Journals
 M. Favalli and M. Dalpasso,
Simulazione di guasti in circuiti integrati digitali ,
Alta Frequenza,
Vol. 4, N. 1, pp. 1322, Gen.Feb. 1992
 M. Dalpasso, M. Favalli, P. Olivo and B. Riccò,
Fault Simulation of Parametric Bridging Faults in CMOS ICs ,
IEEE Transactions on ComputerAided Design of Integrated Circuits and Systems,
Vol. CAD12, pp. 14031410, September 1993
 M. Favalli, M. Dalpasso, P. Olivo and B. Riccò,
Analysis of Resistive Bridging Fault Detection in BiCMOS Digital ICs,
IEEE Transactions on VLSI Systems,
Vol. 1, pp. 342355, September 1993
 M. Dalpasso, M. Favalli, P. Olivo and J. P. Teixeira,
Realistic testability estimates for CMOS ICs,
IEE Electronics Letters,
Vol. 30, N. 19, pp. 15931595, September 15th, 1994
 M. Dalpasso,
Advanced Test Pattern Generation for CMOS I_{DDQ} Testing,
Alta Frequenza,
Vol. 8, N. 2, pp. 5759, Mar.Apr. 1996
 M. Dalpasso, M. Favalli and P. Olivo,
I_{DDQ} Test Invalidation by Break Faults ,
IEE Electronics Letters,
Vol. 32, N. 11, pp. 994995, May 23rd, 1996
 M. Favalli, M. Dalpasso and P. Olivo,
Modeling and Simulation of Broken Connections in CMOS ICs ,
IEEE Transactions on ComputerAided Design of Integrated Circuits and Systems,
Vol. 15, N. 7, pp. 808914, July 1996
 M. Favalli and M. Dalpasso,
Symbolic Handling of Bridging Fault Effects,
Journal of Electronic Testing, Theory and Applications,
Kluwer Academic Publishers,
Vol. 10, N. 3, pp. 271276, June 1997
 M. Dalpasso and M. Favalli,
A Method for Increasing the I_{DDQ} Testability ,
IEEE Transactions on ComputerAided Design of Integrated Circuits and Systems,
Vol. 16, N. 10, pp. 11861188, October 1997
 P. Olivo and M. Dalpasso,
A BIST Scheme for NonVolatile Memories,
Journal of Electronic Testing, Theory and Applications,
Kluwer Academic Publishers,
Vol. 12, N. 1/2, pp. 139144, February/April 1998
 M. Dalpasso, A. Bogliolo and L. Benini,
Virtual Simulation of Distributed IPbased Designs,
IEEE Design & Test of Computers,
Vol. 19, N. 5, pp. 92104, September/October 2002
 M. Favalli and M. Dalpasso,
Bridging Fault Modeling and Simulation for Deep Submicron CMOS ICs,
IEEE Transactions on ComputerAided Design of Integrated Circuits and Systems,
Vol. 21, N. 8, pp. 941953, August 2002
 M. Dalpasso, G. Lancia and R. Rizzi,
The String
Barcoding Problem is NPHard, Lecture Notes in
Computer Science, Vol. 3678 / 2005, pp. 8896
 M. Favalli and M. Dalpasso,
How many
Test Vectors We Need to Detect a Bridging Fault?,
Journal of Electronic Testing, Theory and Applications,
Kluwer Academic Publishers,
Vol. 25, N. 1, pp. 7995, February 2009
 M. Favalli and M. Dalpasso
Applications of Boolean Satisfiability to Verification and Testing of SwitchLevel Circuits,
Journal of Electronic Testing, Springer,
Vol. 30, N. 1, pp. 4155, Febbraio 2014
 L. Valenti, M. Dalpasso and M. Favalli,
Efficient testing of multioutput combinational cells in nanocomplementary metal oxide semiconductor integrated circuits
,
IET Computers & Digital Techniques,
Vol. 8, N. 2, pp. 8389, March 2014
 M. Dalpasso and G. Lancia,
Estimating the strength of poker hands by integer linear programming techniques,
Central European Journal of Operations Research,
Vol. 23, N. 3, pp. 625640, Settembre 2015
 M. Favalli and M. Dalpasso,
Boolean and PseudoBoolean Test Generation for Feedback Bridging Faults,
IEEE Transactions on Computers,
Vol. 65, N. 3, pp. 706715, March 2016
 Conferences with Proceedings
 M. Dalpasso, M. Favalli, P. Olivo and B. Riccò,
SwitchLevel Fault Simulation by CriticalPath Tracing ,
IEEE European Test Conference,
pp. 181190, April 1991
 M. Ambanelli, M. Favalli, M. Dalpasso, P. Olivo and B. Riccò,
Fault Simulation of Multiple Faults in PLAs,
IEEE Annual European Computer Conference (CompEuro),
pp. 229232, May 1991
 M. Favalli, S. Ercolani, M. Dalpasso, P. Olivo and B. Riccò,
Weighted Pseudorandom Generation for BuiltIn SelfTest ,
IEEE Annual European Computer Conference (CompEuro),
pp. 572574, May 1991
 M. Favalli, M. Dalpasso, P. Olivo and B. Riccò,
Analysis of Steady State Detection of Resistive Bridging Faults in BiCMOS Digital
ICs,
IEEE International Test Conference,
pp. 466475, September 1992
 M. Dalpasso, M. Favalli, P. Olivo and B. Riccò,
Parametric Bridging Fault Characterization for the Fault Simulation of
LibraryBased ICs,
IEEE International Test Conference,
pp. 486495, September 1992
 M. Dalpasso, M. Favalli, P. Olivo and B. Riccò,
Influence of IC synthesis on the Random Pattern Testability of Parametric Bridging
Faults,
IEEE European Test Conference,
pp. 398407, April 1993
 M. Favalli, M. Dalpasso, P. Olivo and B. Riccò,
Analysis of Dynamic Effects of Resistive Bridging Faults in CMOS and BiCMOS
Digital ICs,
IEEE International Test Conference,
pp. 865874, October 1993
 M. Favalli, M. Dalpasso, P. Olivo and B. Riccò,
Modeling of Broken Connections Faults in CMOS ICs ,
IEEE European Design and Test Conference,
pp. 159164, FebruaryMarch 1994
 M. Dalpasso, M. Favalli and P. Olivo,
Correlation between IDDQ Testing Quality and Sensor Accuracy,
IEEE European Design and Test Conference,
pp. 568572, March 1995
 M. Dalpasso, M. Favalli and P. Olivo,
Test Pattern Generation for IDDQ: Increasing Test Quality ,
IEEE VLSI Test Symposium,
pp. 304309, AprilMay 1995
 M. Dalpasso and M. Favalli,
Binary Decision Diagrams (BDDs) for the Test Pattern Generation,
IEE International Conference on Software for Electrical Engineering Analysis and
Design,
pp.95104, May 1996
 P. Olivo and M. Dalpasso,
SelfLearning Signature Analysis for NonVolatile Memory Testing,
IEEE International Test Conference,
pp. 303308, October 1996
 M. Dalpasso, A. Bogliolo and L. Benini,
Specification and validation of distributed IPbased designs with JavaCAD,
IEEE/ACM Design Automation and Test in Europe Conference,
pp. 684688, March 1999
 M. Dalpasso, A. Bogliolo and L. Benini,
Virtual Simulation of distributed IPbased designs ,
IEEE/ACM Design Automation Conference,
pp. 5055, June 1999
 M. Dalpasso, A. Bogliolo L. Benini and M. Favalli,
Virtual Fault Simulation of distributed IPbased designs ,
IEEE/ACM Design Automation and Test in Europe Conference 2000,
pp. 99103, March 2000
 M. Dalpasso, A. Bogliolo and L. Benini,
Hardware/Software IP protection,
IEEE/ACM Design Automation Conference 2000,
pp. 593596, June 2000
 M. Favalli and M. Dalpasso,
An evolutionary approach to the design of onchip pseudorandom test pattern
generators,
IEEE/ACM Design Automation and Test in Europe Conference 2002,
March 2002
 F. Bombi, G. Clemente, S. Congiu, M. Dalpasso, F. Filira,
M. Furin, M. Moro, M. Sgargetta and R. Verago,
A new multimedia distributed system for online advanced
teleteaching,
International Conference ICL (Interactive Computer Aided Learning),
September 2005
 F. Bombi, G. Clemente, S. Congiu, M. Dalpasso, F. Filira,
M. Furin, M. Moro, M. Sgargetta and R. Verago,
A new multimedia distributed system for live teaching,
Iadate2006  3rd International Conference on Education,
July 2006
 F. Bombi, G. Clemente, S. Congiu, M. Dalpasso, F. Filira,
M. Furin, M. Moro, M. Sgargetta and R. Verago,
Live teaching with an advanced multimedia distributed system,
IODL2006  2nd International Open & Distance Learning Symposium,
September 2006
 M. Favalli and M. Dalpasso,
High Quality Test Vectors for Bridging Faults in the Presence of
IC's Parameters Variations,
22^{nd} IEEE
International Symposium on Defect and FaultTolerance in VLSI
Systems (DFT '07),
pp. 448456, September 2007
 F. Filira, N Anghelidis and M. Dalpasso,
TeleAssessment of the TeleTaught University Degree in Computer
Science Engineering,
iLearning Forum 2008,
2008
 F. Filira, G. Boccuzzo, M. Dalpasso and N. Anghelidis,
Effectiveness assessment of teletaught vs. traditional courses of a
3year university degree in compuoter science engineering,
INTED2008 International Conference,
March 2008
 M. Dalpasso and G. Lancia,
Computing the equity of a poker hand by Integer Linear Programming,
International Symposium on Operational Research 2013,
September 2013
 M. Dalpasso, D.Bertozzi and M. Favalli,
A Boolean Model for Delay Fault Testing of Emerging Digital Technologies based on Ambipolar Devices,
Design, Automation and Test in Europe (DATE 2018),
pp. 297300, March 2018
 M. Dalpasso e G. Lancia,
New modeling ideas for the exact solution of the closest string problem,
International Workshop on Biological Knowledge Discovery from Data (BIOKDD 2018),
published in Database and Expert Systems Applications,
belonging to series Communications in Computer and Information Science,
pp. 105114, September 2018
 G. Lancia e M. Dalpasso,
Speedingup the Exploration of the 3OPT Neighborhood for the TSP,
International Conference on Optimization and Decision Science (ODS 2018),
published in New Trends in Emerging Complex Real Life Problems,
belonging to series AIRO Springer Series,
pp. 345355, September 2018
 Conferences without Proceedings
 M. Dalpasso,
Approaching the Synthesis for Testable Circuits Beyond the StuckAt Fault Model,
ARCHIMEDES Open Workshop on Synthesis of Testable Circuits ,
Bologna, Italy, February 1994
 M. Dalpasso,
IDDQ Testing di circuiti integrati CMOS,
ELETTRONICA 95  Riunione Annuale del Gruppo di Elettronica del CNR,
Riva del Garda, Trento, Italy, June 1995
 P. Olivo and M. Dalpasso,
SelfLearning Signature Analysis for NonVolatile Memory Testing,
IEEE European Test Workshop,
Montpellier, France, June 1996
 P. Olivo and M. Dalpasso,
A BIST Scheme for NonVolatile Memories,
IEEE International OnLine Testing Workshop,
Biarritz, France, July 1996
 P. Olivo and M. Dalpasso,
A BIST Scheme for NonVolatile Memories,
IEEE NonVolatile Semiconductor Memory Workshop,
Monterey, California, USA, February 1997
 G. Lancia, M. Dalpasso e R. Rizzi,
The String
Barcoding Problem is NPHard, RECOMB 2005 Satellite
Workshop on Comparative Genomics, Settembre 2005
 Thesis for Laurea Degree in Electronic Engineering
 Simulazione a livello switch di circuiti integrati CMOS,
February 21st, 1990, Bologna, Italy.
 Thesis for Ph.D. in Electronic Engineering and Computer Science
 Analisi, Modellistica e Simulazione di Guasto in Circuiti Integrati CMOS,
July 25th, 1994, Rome, Italy.

