Postdoctoral Researcher
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Department of Information Engineering University of Padova Via Gradenigo 6/B, 35131 Padova, Italy Tel: +39 049 827 7954 Fax: +39 049 827 7799 Room: 418 DEI/G E-mail: silvest1 ♦ dei • unipd • it (♦=at, •=dot) Skype: yuri_rwx Linkedin: my profile Curriculum: pdf (last update February 12, 2013) |
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I am looking for an academic or industrial research position, please download my curriculum (pdf). Research and teaching statemens are available upon request.
Main Research Interests
- Resilient Algorithms. Memories are susceptible to faults, where the logical state of one or multiple bits is read differently from how it was last written. Coping with memory faults appears to be of particular importance for all those applications handling massive data sets. Unfortunately, most applications are far from being tolerant to faults and hardware solutions (e.g., ECC memories) are very expensive. To cope with this, a recent trend is to design algorithms and data structures that are more resilient to faults (a survey here). I'm working on the design and analysis of resilient algorithms and data structures, with particular emphasis to faults on memory hierarchies. A my published work on the topic appeared at FSTTCS 2011.
- Algorithms and models for MapReduce. In recent years, MapReduce has emerged as a computational paradigm for processing large-scale data sets in a series of rounds executed on conglomerates of commodity servers. The MapReduce framework has been widely adopted by a number of large web companies and in several other applications (e.g., GPU and multicore processing), however just a few works have studied the paradigm in a rigorously way (see here, here, here). I'm carrying out research on fundamental algorithmic issues arising in the MapReduce framework. A preliminary result appeared at ICS 2012.
- Memory hierarchy. A typical modern platform features a hierarchical cascade of memories whose capacities and access times increase as they grow farther from the CPU. In order to amortize the larger cost incurred when referencing data in distant levels of the hierarchy, blocks of contiguous data are replicated across the faster levels, either automatically by the hardware (e.g., in the case of RAM-cache interaction) or by software (e.g., in the case of disk-RAM interaction). The rationale behind such a hierarchical organization is that the memory access costs of a computation can be reduced when the same data are frequently reused within a short time interval, and data stored at consecutive addresses are involved in consecutive operations, two properties known as temporal and spatial locality of reference, respectively. I have worked on algorithms for memory hierarchies, with particular emphasis to cache-oblivious algorithms, that is, algorithms that do not make explicit use of the parameters of the memory hierarchy but still run efficiently. Some my published results are TGC 2006, TCS 2008, J. Proc 2010.
- Communication hierarchy. Parallel algorithms have become a mainstream concern due to the increasing amount of data to be processed and to the sequential architectures reaching physical limitation as they are constrained by the speed of light and thermodynamics laws. Communication is a major factor determining the performance of parallel algorithms and then algorithms should exploit the communication hierarchy induced by the interconnection system in order to reduce communication. My research has been focused on the study of oblivious algorithms in parallel settings, that is, algorithms that do not make explicit use of parameters characterizing the interconnection system but still run efficiently. Some my published works are EURO-PAR 2012, IPDPS 2010, IPDPS 2007, APDCM 2006
Brief Bio
I received the Laurea degree summa cum laude (2005) and the Ph.D. degree (2009) both in Computer Engineering from the University of Padova and under the supervision of Prof. Andrea Pietracaprina. From 2007 to 2008, I visited the Department of Computer Science of the University of Texas at Austin, under the supervision of Prof. Vijaya Ramachandran. In 2010, I won the IPDPS Best Paper Award in the Algorithmic Track for the paper "Oblivious Algorithms for Multicores and Network of Processors", coauthored with A. Chowdhury, B. Blakeley, and V. Ramachandran. In summer 2011, I visited the MADALGO Center in Denmark. I have been in the program committees of IEEE BigData 2013, IEEE IPDPS 2013, and ACM/IEEE SC 2013 (Poster section). I have also served in the organizing committees of 27th IEEE IPDPS 2013, 26th ACM ICS 2012, 7th ESSIR 2009. Since 2009, I have been a Postdoctoral Research Associate at the Department of Information Engineering of the University of Padova.
Are you looking forward to learn more about me? Please, download my curriculum! :-) pdf
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