Sunday, September 23
17:00-20:00Check-in & Reception (Via Frangipane, 4)
19:30-21:00Welcome Buffet (“Center Canteen” - Via Frangipane, 2)

Monday, September 24
07:30-08:45Breakfast (“Center Canteen”)
08:30-08:45Registration (“Fresco Room” - La Rocca, Via Frangipane, 6)
09:00-09:30Using AI to Transform Informational Videos and Our Watching Behavior
 Manish Gupta (VideoKen and IIIT Bangalore, India)
09:30-10:00Aspects of provenance and performance for computational workflows for HPC
 Line Pouchard (Brookhaven National Laboratory, NY, USA)
10:00-10:30Towards tools for performance bottleneck analysis
 Saday Sadayappan (Ohio State University, OH 43210, USA)
11:00-11:30Experience in scaling performance-portable weather and climate applications
 Mauro Bianco (CSCS Lugano, Switzerland)
11:30-12:00Manycore/Multicore Parallel Traversal of Large Ensembles of Decision Trees for HPC
 Salvatore Orlando (Ca’ Foscari University of Venice, Italy)
12:00-12:30Adaptive MapReduce Similarity Joins
 Francesco Silvestri (University of Padova, Italy)
13:00-14:30Lunch (“Center Canteen”)
14:30-15:00Program Generation for Small-Scale Linear Algebra
 Markus Püschel (ETH Zürich, Switzerland)
15:00-15:30A model-driven approach for a new generation of adaptive libraries
 Flavio Vella (Free U. of Bozen, Italy)
15:30-16:00Automatic Tuning of Stencil Computations with Ordinal Regression
 Biagio Cosenza (T.U. Berlin, Germany)
16:00-16:30LORE: A Loop Repository for the Evaluation of Compilers and other Educational Applications
 Alex Nicolau and Alex Veidenbaum (University of California, Irvine, USA)
17:00-18:30Discussion Session I: Software performance
 Coordinators: L. Pouchard, S. Sadayappan
19:00-19:30Bus Trip from Bertinoro to restaurant
19:30-22:00Dinner, La divina bistecca, Via Sendi Fratelli 8, 47034 Forlimpopoli, FC, Italy, (+39 0543 562942).

Tuesday, September 25
07:30-08:45Breakfast (“Center Canteen”)
09:00-09:30Accelerating general purpose parallel computing with the TPA architecture
 Martti Forsell (VTT, Finland)
09:30-10:00Accelerating Dense Matrix Multiplication through DataFlow-Threads (DF-Threads)
 Roberto Giorgi (University of Siena, Italy)
10:00-10:30A collective communication model for WK-recursive network topologies
 Lorenzo Verdoscia (CNR-ICAR Napoli, Italy)
11:00-12:30Discussion Session II: What is special about ML computations?
 Coordinators: M. Püschel, C. Trinitis
12:30-14:00Lunch (“Center Canteen”)
14:30-18:30Excursion to Ravenna
19:30-22:00Social Dinner, Grand Hotel Cesenatico, Piazza Andrea Costa 1, 47042 Cesenatico (0547 80012).

Wednesday, September 26
07:30-08:45Breakfast (“Center Canteen”)
09:00-09:30Theory of Accelerator Computing
 Bill McColl (Huawei, Paris, France)
09:30-10:00Power Modeling of Heterogeneous Mobile SoCs using Machine Learning
 Ben Juurlink (T.U. Berlin, Germany)
10:00-10:30MemComputing with self-organizing logic gates
 Massimiliano Di Ventra (University of California, San Diego, USA)
11:00-11:30Are existing Parallel Programming Models ready for Future HPC Systems?
 Josef Weidendorfer (Leibniz Supercomputing Centre and T.U. Munich, Germany)
11:30-12:00How to spot Linear Algebra in Spreadsheets
 Nicolai Stawinoga (Imperial College, London, United Kingdom)
12:00-12:30On the Use of Data Mining for multi-dimensional Sensor Data
 Carsten Trinitis and Amir Raoofy (T.U. Munich, Germany)
12:30-14:00Lunch (“Center Canteen”)
14:30-15:00Implementing the GraphBLAS C API
 Jose Moreira (IBM Research, NY, USA)
15:00-15:30Components for a High Performance GraphBLAS
 Richard Veras (Louisiana State University, Baton Rouge, LA, USA)
16:00-17:30Discussion Session III: Computing paradigms
 Coordinators: M. Gupta, B. McColl
19:30-21:30Dinner, Ca’ de Bè Osteria Enoteca, Piazza della Libertà, 9/b, 47032 Bertinoro FC, 0543 444435.

Thursday, September 27
07:30-08:30Breakfast (“Center Canteen”)
08:30-09:00Tensor Comprehensions for Machine Learning in SaC
 Sven-Bodo Scholz (Heriot-Watt University, United Kingdom)
09:00-09:30From HPC to Data Analytics: The Challenges Ahead
 Wolfgang Nagel (T.U. Dresden, Germany)
09:30-10:00Going from C to stream-like RTL implementations for FPGA acceleration
 Alain Darte (Xilinx, San Jose, California, USA)
10:00-10:30Efficient Implementation of Unconstrained Submodular Function Minimization
 Tyler Smith (ETH Zürich, Switzerland)
11:00-11:30The I/O complexity of Strassen’s matrix multiplication
 Gianfranco Bilardi (University of Padova, Italy)
11:30-13:00Discussion Session IV: Linear algebra
 Coordinators: J. Moreira, B. Scholtz
13:00-14:30Lunch (“Center Canteen”)
19:30-21:30Dinner (“Center Canteen”)