EXPRESS: A Rapid Prototyping/Development Environment for Embedded Computer Systems

Data e Ora : Thursday, July 3, 2003 - 09:00
Relatore : Dr. Alex Nicolau
Affiliazione : University of California at Irvine (USA)
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In this talk we will describe the EXPRESS environment developed at the University of California, Irvine over the last five years, drawing on our research experience in the preceeding decade. EXPRESS combines a sophisticated, highly optimizing, highly retargetable compiler with a similarly retargetable simulation environment. Using a new architectural description language (EXPRESSION) the environment can be rapidly and accurately retargeted to a variety of computer systems, that include complex processing units (ILP suprescalar/vliw highly-pipelined architectures), with complex memory organizations (multiple register files, on-chip and off chip, directly addressable sram, various memory accessing modes, caches, etc) and idiosynchratic system organizations (co-processors, complex bus structures, special-purpose operations, add-on units, etc). EXPRESS therefore allows the quick generation of cycle-accurate simulators together with highly optimized compilers that `track` changes (introduced by the architect/designer) in the complex, realistic, architecture, and provides visual and quantitative tools to quickly evaluate cost/benefit ratios of such changes with respect to performance, power consumption and hardware/area cost. Thus, our environment holds, perhaps for the first time, the promise of truly meaningful architectural exploration and thereby potentially better system designs, while simultaneously (significantly) shortening the design cycle.

An Overview of the BlueGene/L Supercomputer

Data e Ora : Monday, February 10, 2003 - 15:30
Relatore : Dr. Manish Gupta
Affiliazione : IBM T. J. Watson Research Center
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In this talk, we will give an overview of the BlueGene/L Supercomputer, being developed as part of a research partnership between IBM and the Lawrence Livermore National Laboratory. This massively parallel system of 65,536 nodes is based on a new architecture that exploits system-on-a-chip technology to deliver target peak processing power of 360 teraFLOPS (trillion floating-point operations per second). The machine is scheduled to be operational in the 2004-2005 time frame, at price/performance and power consumption/performance targets unobtainable with conventional architectures. We describe the challenges in designing a system software infrastructure that scales to 65,536 nodes, and how we have approached these challenges. We describe early experience with a small BlueGene/L prototype running in our laboratory.