In advanced CMOS VLSI technologies the critical dimensions are well below 100nm. For such technologies, the use of smart Design for Manufacturing techniques and corresponding technology optimization, which one can call `Manufacturing for Design`, is becoming mandatory in order to achieve
reasonable yields. Variations in the main transistor characteristics are coming from different sources in random and systematic process variability. 3D process-effects, subwavelength-lithography and stress effects are the most important.
In this scenario TCAD is an invaluable tool for understanding the physics behind the various phenomena and to quantitatively characterize the expected impact of each effect and their interactions. Using TCAD, it is possible to study by means of 3D simulations the behavior of small devices, the impact of stress effects and of non-uniform gate shapes on the final characteristics of a transistor. In this talk an approach with full 3D process-device simulations and its influence on the development of a TCAD-to-circuit simulation flow will be presented.